Model Selection

Verilog code generation

# Verilog code generation

Verireason Qwen2.5 7b RTLCoder Verilog GRPO Reasoning Tb I1 GGUF

This is a 7B-parameter large language model optimized for Verilog hardware description language, specializing in RTL coding and reasoning tasks, with multiple quantization versions available.

Large Language Model

Transformers English

Verireason Qwen2.5 7b RTLCoder Verilog GRPO Reasoning Tb GGUF

This is a quantized model based on Qwen2.5-7b, specializing in Verilog code generation and reasoning tasks, optimized using reinforcement learning techniques.

Large Language Model

Transformers English

Verireason Codellama 7b RTLCoder Verilog GRPO Reasoning Tb

VeriReason is a Verilog RTL code generation method that combines reinforcement learning with testbench feedback, significantly improving the performance of pre-trained models in the field of hardware design.

Large Language Model

Codev R1 Distill Qwen 7B

A Verilog RTL code generation model distilled from DeepSeek-R1, demonstrating outstanding performance in Verilog benchmarks

Large Language Model

Fine Tuned Codegen 16B Verilog

VeriGen is a fine-tuned 16B parameter model based on CodeGen-multi-16B, specifically designed for generating Verilog hardware description language code.

Large Language Model

Transformers Other

Fine Tuned Codegen 6B Verilog

VeriGen is a 6B-parameter model fine-tuned from CodeGen-multi-16B, specifically designed for generating Verilog hardware description language code.

Large Language Model

Transformers Other

Fine Tuned Codegen 2B Verilog

VeriGen is a 2 billion parameter model fine-tuned from CodeGen-multi-2B, specifically designed for generating Verilog Hardware Description Language code.

Large Language Model

Transformers Other

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