Fine Tuned Codegen 6B Verilog

🚀 VeriGen

The VeriGen model is a fine - tuned version for Verilog code generation, offering capabilities in generating Verilog snippets based on given contexts.

🚀 Quick Start

The VeriGen model is ready for text - generation tasks. You can use it by following the steps in the "Use" section.

✨ Features

• Fine - tuned for Verilog: Trained on a Verilog code dataset, it can generate relevant Verilog code.
• Based on a strong baseline: Built upon the CodeGen - multi - 16B model.

📦 Installation

No specific installation steps are provided in the original document.

💻 Usage Examples

Basic Usage

# pip install -q transformers
import torch
from transformers import AutoTokenizer, AutoModelForCausalLM
# Prompt
prompt = "//module half adder "
device='cuda'
# Load model and tokenizer
model_name = "shailja/fine - tuned - codegen - 6B - Verilog"
tokenizer = AutoTokenizer.from_pretrained(model_name)
model = AutoModelForCausalLM.from_pretrained(model_name).to(device)

# Sample
input_ids = tokenizer(prompt, return_tensors="pt").input_ids.to(device)
sample = model.generate(input_ids, max_length=128, temperature=0.5, top_p=0.9)

print(tokenizer.decode(sample[0], truncate_before_pattern=[r"endmodule"]) + "endmodule")

Intended use

The model was trained on Verilog from GitHub and textbooks. As such it is not an instruction model and commands like "Write a module that implements a 2 - to - 1 Mux." do not work well. However, by adding a partial line of module header like "module mux" in addition with the text in the prompt turns it into a capable Verilog teaching assistant.

Feel free to share your generations in the Community tab!

Attribution & Other Requirements

The pretraining dataset of the model was not filtered for permissive licenses only. Nevertheless, the model can generate source code verbatim from the dataset. The code's license might require attribution and/or other specific requirements that must be respected.

📚 Documentation

Model Summary

The VeriGen model is a 6B parameter fine - tuned version of CodeGen - multi - 16B trained on Verilog code dataset.

Limitations

The model has been trained on Verilog source code from open sources. The predominant natural language in source code is English, although other languages are also present. As such the model is capable of generating Verilog snippets provided some context but the generated code is not guaranteed to work as intended. It can be inefficient, contain bugs or exploits. See [the paper](https://drive.google.com/file/d/1cN - b9GnWtHzQRoE7M7gAEyivY0kl4BYs/view) for an in - depth discussion of the model limitations.

Training

Model

• Architecture: GPT - 2 model with multi - query attention
• Pretraining steps: 150k
• Pretraining tokens: ~72B
• Precision: fp16

Hardware

• GPUs: 4 Tesla A100
• Training time: 10 days

🔧 Technical Details

The VeriGen model is based on the fine - tuning of the CodeGen - multi - 16B model. It uses a GPT - 2 architecture with multi - query attention and is trained on a Verilog code dataset from GitHub and textbooks. The training process involves 150k pretraining steps with approximately 72B tokens and is carried out on 4 Tesla A100 GPUs for 10 days.

📄 License

The model is licensed under the BigCode OpenRAIL - M v1 license agreement. You can find the full agreement [here](https://huggingface.co/spaces/bigcode/bigcode - model - license - agreement).

📚 Citation

@misc{https://doi.org/10.48550/arxiv.2212.11140,
  doi = {10.48550/ARXIV.2212.11140},
  url = {https://arxiv.org/abs/2212.11140},
  author = {Thakur, Shailja and Ahmad, Baleegh and Fan, Zhenxing and Pearce, Hammond and Tan, Benjamin and Karri, Ramesh and Dolan - Gavitt, Brendan and Garg, Siddharth},
  title = {Benchmarking Large Language Models for Automated Verilog RTL Code Generation},
  publisher = {arXiv},
  year = {2022},
  copyright = {arXiv.org perpetual, non - exclusive license}
}